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ADVANCED LINEAR DEVICES, INC.
ALD2721E/ALD2721
DUAL EPADTM MICROPOWER OPERATIONAL AMPLIFIER
KEY FEATURES * EPAD ( Electrically Programmable Analog Device) * User programmable VOS trimmer * Computer-assisted trimming * Rail-to-rail input/output * Compatible with standard EPAD Programmer * Each amplifier VOS can be trimmed to a different Vos level * High precision through in-system circuit trimming * Reduces or eliminates VOS, PSRR, CMRR and TCVOS errors * System level "calibration" capability * Application Specific Programming mode * In-System Programming mode * Electrically programmable to compensate for external component tolerances * Achieves 0.01pA input bias current and 35V input offset voltage with micropower * Low voltage operation GENERAL DESCRIPTION The ALD2721E/ALD2721 is a dual monolithic rail-to-rail precision CMOS operational amplifier with integrated user programmable EPAD (Electrically Programmable Analog Device) based offset voltage adjustment. The ALD2721E/ALD2721 is a dual version of the ALD1721E/ALD1721 operational amplifier. Each ALD2721E/ALD2721 operational amplifier features individual, user-programmable offset voltage trimming resulting in significantly enhanced total system performance and user flexibility. EPAD technology is an exclusive ALD design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. It utilizes CMOS FETs as in-circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. Once programmed, the set parameters are stored indefinitely. EPAD offers the circuit designer a convenient and cost-effective trimming solution for achieving the very highest amplifier/ system performance. The ALD2721E/ALD2721 dual operational amplifier features rail-to-rail input and output voltage ranges, tolerance to overvoltage input spikes of 300mV beyond supply rails, capacitive loading up to 50pF, extremely low input currents of 0.01pA typical, high open loop voltage gain, useful bandwidth of 700KHz, slew rate of 0.7V/s, and low typical supply current of 200A for both amplifiers. ORDERING INFORMATION
Operating Temperature Range -55C to +125C 14-Pin CERDIP Package ALD2721E DB ALD2721 DB 0C to +70C 14-Pin Small Outline Package (SOIC) ALD2721E SB ALD2721 SB 0C to +70C 14-Pin Plastic Dip Package ALD2721E PB ALD2721 PB
BENEFITS * * * * * * * * * * Eliminates manual and elaborate system trimming procedures Remote controlled automated trimming In-System Programming capability No external components No internal clocking noise source Simple and cost effective Small package size Extremely small total functional volume size Low system implementation cost Micropower
APPLICATIONS * * * * * * * * * * * * * * Sensor interface circuits Transducer biasing circuits Capacitive and charge integration circuits Biochemical probe interface Signal conditioning Portable instruments High source impedance electrode amplifiers Precision Sample and Hold amplifiers Precision current to voltage converter Error correction circuits Sensor compensation circuits Precision gain amplifiers Periodic In-system calibration System output level shifter
PIN CONFIGURATION
-IN A +IN A VN/C N/C +IN B -IN B
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VE 2A VE 1A OUT A V+ OUT B VE 1B VE 2B
TOP VIEW DB, PB, SB PACKAGE
* Contact factory for industrial temperature range
(c) 1998 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
FUNCTIONAL DESCRIPTION The ALD2721E/ALD2721 utilizes EPADs as in-circuit elements for trimming of offset voltage bias characteristics. Each ALD2721E/ALD2721 operational amplifier has a pair of EPAD-based circuits connected such that one circuit is used to adjust V OS in one direction and the other circuit is used to adjust VOS in the other direction. While each of the basic EPAD devices is monotonically adjustable, the VOS of the ALD2721E can be adjusted many times in both directions. Once programmed, the set VOS levels are stored permanently, even when the device is removed. Functional Description of ALD2721E The ALD2721E is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. It also has a guaranteed offset voltage program range, which is ideal for applications that require electrical offset voltage programming. The ALD2721E is an operational amplifier that can be trimmed stand-alone, with user application-specific programming or insystem programming conditions. User application-specific circuit programming refers to a situation where the Total Input Offset Voltage of the ALD2721E can be trimmed with the actual intended operating conditions. Take the example of an application circuit that uses + 1V and -1V power supplies, an operational amplifier input biased at +1V, and an average operating temperature at +85C; the circuit can be wired up to these conditions within an environmental chamber with the ALD2721E inserted into a test socket while it is being electrically trimmed. Any error in VOS due to these bias conditions can be automatically zeroed out. The Total VOS error is now limited only by the adjustable range and the stability of VOS, and the input noise voltage of the operational amplifier. This Total Input Offset Voltage now includes V OS, as VOS is traditionally specified; plus the VOS error contributions from PSRR, CMRR, TCV OS, and noise. Typically, this Total VOS error term ranges approximately 35V for the ALD2721E. In-System Programming refers to the condition where the EPAD adjustment is made after the ALD2721E has been inserted into a circuit board. In this case, the circuit design must provide for the ALD2721E to operate in both normal mode and in programming mode. One of the benefits of in-system programming is that not only the ALD2721E offset voltage from operating bias conditions has been accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be programmed and corrected. In this way, the "in-system" circuit output can be adjusted to a desired level eliminating need for another trimming function.
Functional Description of ALD2721 The ALD2721 is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. The ALD2721 offers similar programmable features as the ALD2721E, but with more limited offset voltage program range. It is intended for standard operational amplifier applications where little or no electrical programming by the user is necessary. USER PROGRAMMABLE VOS FEATURE Each ALD2721E/ALD2721 has four additional pins, compared to a conventional dual operational amplifier which has eight pins. These four additional pins are named VE1A, VE2A for op amp A and VE1B, VE2B for op amp B. Each of these pins VE1A, VE2A, VE1B, VE2B (represented by VExx) are connected to a separate, internal offset bias circuit. VExx pins have initial internal bias voltage values of approximately 1 to 2 Volts. The voltage on these pins can be programmed using the ALD E100 EPAD Programmer and the appropriate Adapter Module. The useful programming range of voltages on VExx pins are 1 Volt to 3 Volts. VExx pins are programming pins, used during electrical programming mode to inject charge into the internal EPADs. Increasing voltage on VE1A/VE1B increases the offset voltage whereas increasing voltage on VE2A/VE2B decreases the offset voltage of op amp A and op amp B, respectively. The injected charge is then permanently stored. After programming, VExx pins must be left open in order for these voltages to remain at the programmed levels. During programming, voltages on VExx pins are increased incrementally to program the offset voltage of the operational amplifier to the desired VOS. Note that desired VOS can be any value within the offset voltage programmable ranges, and can be either equal zero, a positive value or a negative value. This VOS value can also be reprogrammed to a different value at a later time, provided that the useful VE1x or VE2x programming voltage range has not been exceeded. VExx pins can also serve as capacitively coupled input pins. Internally, VE1 and VE2 are programmed and connected differentially. Temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer. While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by the EPAD Programmer. In-system programming requires the ALD2721E application circuit to accommodate these programming pulses. This can be accomplished by adding resistors at certain appropriate circuit nodes. For more information, see Application Note AN1700.
2
Advanced Linear Devices
ALD2721E/ALD2721
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+ Differential input voltage range Power dissipation Operating temperature range PB,SB package DB package Storage temperature range Lead temperature, 10 seconds 13.2V -0.3V to V+ +0.3V 600 mW 0C to +70C -55C to +125C -65C to +150C +260C
OPERATING ELECTRICAL CHARACTERISTICS TA = 25oC VS = 2.5V unless otherwise specified
2721E Typ 2721 Typ
Parameter Supply Voltage
Symbol VS V+ VOS i VOS VOS
Min 1.0 2.0
Max 5.0 10.0
Min 1.0 2.0
Max 5.0 10.0
Unit V V V mV
Test Conditions
Single Supply RS 100K
Initial Input Offset Voltage 1 Offset Voltage Program Range 2 Programmed Input Offset Voltage Error 3 Total Input Offset Voltage 4
35 5 7 50
100 0.5 100
50 2 50
150
150
V
At user specified target offset voltage At user specified target offset voltage TA = 25C 0C TA +70C TA = 25C 0C TA +70C V+ = +5V VS = 2.5V
VOST
50
100
50
150
V
Input Offset Current 5
IOS
0.01
10 240
0.01
10 240
pA pA pA pA V V V/C dB
Input Bias Current 5
IB
0.01
10 240 5.3 +2.8 -0.3 -2.8
0.01
10 240 5.3 +2.8
Input Voltage Range 6
VIR
-0.3 -2.8 10 14 7 90
Input Resistance Input Offset Voltage Drift 7 Initial Power Supply Rejection Ratio 8 Initial Common Mode Rejection Ratio 8 Large Signal Voltage Gain
RIN TCVOS PSRR i
1014 7 90
RS 100K RS 100K
CMRR i
90
90
dB
RS 100K
AV
15 10
100
15 10 0.01 4.99 -2.40 2.40
100
V/mV V/mV 0.01 V V V V mA
RL =100K 0C TA +70C R L =1M V =5V 0C TA +70C R L =100K 0C TA +70C
Output Voltage Range
VO low VO high VO low VO high
4.99
0.001 4.999 -2.48 2.48 1
0.001 4.999 -2.48 2.48 1
-2.40
2.40
Output Short Circuit Current
ISC
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
ALD2721E/ALD2721
Advanced Linear Devices
3
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) TA = 25 oC V S = 2.5V unless otherwise specified
2721E Typ 200 2721 Typ 200
Parameter Supply Current
Symbol IS
Min
Max 400
Min
Max 400
Unit A
Test Conditions VIN = 0V No Load VS = 2.5V
Power Dissipation Input Capacitance Maximum Load Capacitance Equivalent Input Noise Voltage Equivalent Input Noise Current Bandwidth Slew Rate
PD CIN CL en in BW SR
1.00 1 50 55 0.6 700 0.7
2.00
1.00 1 50 55 0.6 700 0.7
2.00
mW pF pF nV/Hz fA/Hz KHz V/s
f = 1KHz f =10Hz
AV = +1 RL = 100K RL = 100K RL =100K CL =50pF 0.1% AV = -1 RL = 100K CL = 50pF AV =100
Rise time Overshoot Factor
tr
0.2 20
0.2 20
s %
Settling Time
tS
10
10
s
Channel Separation
CS
140
140
dB
TA = 25oC VS = 2.5V unless otherwise specified
2721E
Parameter Average Long Term Input Offset Voltage Stability 9 Initial VE Voltage Symbol VOS time VE1 i, VE2 i Min Typ 0.02 Max Min
2721
Typ 0.02 Max Unit V/ 1000 hrs V Test Conditions
1.2
1.7
Programmable Change of VE Range Programmed VE Voltage Error
VE1, VE2
1.5
2.5
1.0
V
e(VE1-VE2)
0.1
0.1
%
VE Pin Leakage Current
ieb
-5
-5
A
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
4
Advanced Linear Devices
ALD2721E/ALD2721
V S = 2.5V -55C TA +125C unless otherwise specified
2721E
Parameter Initial Input offset Voltage Input Offset Current Input Bias Current Initial Power Supply Rejection Ratio 8 Initial Common Mode Rejection Ratio 8 Large Signal Voltage Gain Output Voltage Range Symbol VOS i IOS IB PSRR i 85 Min Typ 0.7 2.0 2.0 85 Max Min
2721
Typ 0.7 2.0 2.0 Max Unit mV nA nA dB RS 100K Test Conditions RS 100K
CMRR i
83
83
dB
RS 100K
AV VO low VO high
15
50 -2.47 2.45 -2.40
15
50 -2.47 2.45 -2.40
V/mV V V
RL = 100K
2.35
2.35
R L = 100K
TA = 25 oC V S = 5.0V unless otherwise specified
2721E
Parameter Initial Power Supply Rejection Ratio 8 Initial Common Mode Rejection Ratio
8
2721
Max Min Typ 85 Max Unit dB Test Conditions RS 100K
Symbol PSRR i
Min
Typ 85
CMRRi
83
83
dB
RS 100K
Large Signal Voltage Gain Output Voltage Range
AV VO low VO high BW SR
250 -4.98 4.98 1.0 1.0 -4.90 4.90
250 -4.98 4.98 1.0 1.0 -4.90
V/mV V
RL = 100K R L = 100K
4.90
Bandwidth Slew Rate
MHz V/s AV = +1, CL = 50pF
ALD2721E/ALD2721
Advanced Linear Devices
5
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE
OUTPUT VOLTAGE SWING (V)
6
OPEN LOOP VOLTAGE GAIN (V/mV)
OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE
1000
5 4 3 2 1 0
25C TA +125C RL = 100K
100
10 55C TA +125C RL = 100K 1 2 4 SUPPLY VOLTAGE (V) 6 8
1
2
3
4
5
6
7
0
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE
1000
SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE
INPUTS GROUNDED OUTPUT UNLOADED TA = -55C 400 300 +70C 200 0 +125C +25C -25C
INPUT BIAS CURRENT (pA)
SUPPLY CURRENT (A)
100 10
VS = 2.5V
500
1.0
0.1 0.01 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C)
0
1
2 3 4 SUPPLY VOLTAGE (V)
5
6
ADJUSTMENT IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2
ADJUSTMENT IN INPUT OFFSET VOLTAGE VOS (mV)
10 8
120
OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF FREQUENCY
100 80 60 40 20 0 -20 0 45 90 135 180 1 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M VS = 2.5V TA = 25C
OPEN LOOP VOLTAGE GAIN (dB)
PHASE SHIFT IN DEGREES
6 4 2 0 -2 -4 -6 -8 -10 0.50 0.75 1.00 1.25 1.50 1.75 2.00 CHANGE IN VE1 AND VE2 (V)
VE2 VE1
6
Advanced Linear Devices
ALD2721E/ALD2721
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE
7 6
LARGE - SIGNAL TRANSIENT RESPONSE
2V/div VS = 1.0V TA = 25C RL = 100K CL = 50pF
COMMON MODE INPUT VOLTAGE RANGE (V)
5 4 3 2 1 0 0
TA = 25C
500mV/div
1 2 3 4 5 6 7
5s/div
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF LOAD RESISTANCE
1000
SMALL - SIGNAL TRANSIENT RESPONSE
100mV/div VS = 2.5V TA = 25C RL = 100K CL = 50pF
OPEN LOOP VOLTAGE GAIN (V/mV)
100
10 VS = 2.5V TA = 25C 1 10K 100K 1M 10M
20mV/div
2s/div
LOAD RESISTANCE ()
LARGE - SIGNAL TRANSIENT RESPONSE
100
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE BEFORE AND AFTER EPAD PROGRAMMING
EXAMPLE B: VOST AFTER EPAD PROGRAMMING VOST TARGET = -750V EXAMPLE A: VOST AFTER EPAD PROGRAMMING VOST TARGET = 0.0V
PERCENTAGE OF UNITS (%)
5V/div
VS = 2.5V TA = 25C RL = 100K CL = 50pF
80
60 VOST BEFORE EPAD PROGRAMMING
40
20
2V/div
5s/div
0 -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500
TOTAL INPUT OFFSET VOLTAGE (V)
ALD2721E/ALD2721
Advanced Linear Devices
7
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE (V)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500 PSRR = 80 dB 400 EXAMPLE A: VOS EPAD PROGRAMMED AT VSUPPLY = +5V EXAMPLE B: VOS EPAD PROGRAMMED AT VSUPPLY = +8V
300
200
100
0 0 1 2 3 4 5 6 7 8 9 10
SUPPLY VOLTAGE (V)
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500 VSUPPLY = 5V CMRR = 80dB 400
300
200
EXAMPLE B: VOS EPAD PROGRAMMED AT VIN = -4.3V
EXAMPLE A: VOS EPAD PROGRAMMED AT VIN = 0V
100
0 -5 -4 -3 -2 -1 0
EXAMPLE C: VOS EPAD PROGRAMMED AT VIN = +5V 1 2 3 4 5
COMMON MODE VOLTAGE (V)
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50 COMMON MODE VOLTAGE RANGE OF 0.5V 40
30 VOS EPAD PROGRAMMED AT COMMON MODE VOLTAGE OF 0.25V
20 CMRR = 80dB 10
0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
COMMON MODE VOLTAGE (V)
8
Advanced Linear Devices
ALD2721E/ALD2721
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions
2500
TOTAL INPUT OFFSET VOLTAGE (V)
2500
TOTAL INPUT OFFSET VOLTAGE (V)
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE A VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE B VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
+
X
+
X
2500
2500
TOTAL INPUT OFFSET VOLTAGE (V)
TOTAL INPUT OFFSET VOLTAGE (V)
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE C VOS BUDGET AFTER EPAD PROGRAMMING VOS BUDGET BEFORE EPAD PROGRAMMING
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE D VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
+
X
+
X
Device input VOS PSRR equivalent VOS
Total Input VOS after EPAD Programming
+
X
CMRR equivalent VOS TA equivalent VOS Noise equivalent VOS External Error equivalent VOS
ALD2721E/ALD2721
Advanced Linear Devices
9
DEFINITIONS AND DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the ALD2721E/ALD2721 operational amplifier when shipped from the factory. The device has been pre-programmed and tested for programmability. 2. Offset Voltage Program Range is the range of adjustment of user specified target offset voltage. This is typically an adjustment in either the positive or the negative direction of the input offset voltage from an initial input offset voltage. The input offset programming pins, VE1A/VE1B or VE2A/VE2B change the input offset voltages in thepositive or negative direction, for each of the amplifier A or B, respectively. User specified target offset voltage can be any offset voltage within this programming range. 3. Programmed Input Offset Voltage Error is the final offset voltage error after programming when the Input Offset Voltage is at target Offset Voltage. This parameter is sample tested. 4. Total Input Offset Voltage is the same as Programmed Input Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, PSRR, CMRR, TCVOS and noise. It can also include errors introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. This parameter is sample tested. 5. The Input Offset and Bias Currents are essentially input protection diode reverse bias leakage currents. This low input bias current assures that the analog signal from the source will not be distorted by it. For applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage having a separate input offset voltage. While Total Input Offset Voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one user selected input bias voltage. Depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. For the ALD2721E/ ALD2721, the switching point between the two stages occur at approximately 1.5V below positive supply voltage. 7. Input Offset Voltage Drift is the average change in Total Input Offset Voltage as a function of ambient temperature. This parameter is sample tested. 8. Initial PSRR and initial CMRR specifications are provided as reference information. After programming, error contribution to the offset voltage from PSRR and CMRR is set to zero under the specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error. 9. Average Long Term Input Offset Voltage Stability is based on input offset voltage shift through operating life test at 125C extrapolated to TA = 25 C, assuming activation energy of 1.0eV. This parameter is sample tested.
10
ADDITIONAL DESIGN NOTES: A. The ALD2721E/ALD2721 is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 70 degrees of phase margin at unity gain frequency. A unity gain buffer using the ALD2721E/ALD2721 will typically drive 50pF of external load capacitance. B. The ALD2721E/ALD2721 has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail-to-rail input common mode voltage range. The switching point between the two differential stages is 1.5V below positive supply voltage. For applications such as inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5V operation), the common mode voltage does not make excursions below this switching point. However, this switching does take place if the operational amplifier is connected as a railto-rail unity gain buffer and the design must allow for input offset voltage variations. C. The output stage consists of class AB complementary output drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD2721E/ALD2721 an effective analog signal buffer for high source impedance sensors, transducers, and other circuit networks. D. The ALD2721E/ALD2721 has static discharge protection. Care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages not to exceed 0.3V of the power supply voltage levels. E. VExx are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. For some applications, these terminals may need to be shielded from external coupling sources. For example, digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout to place ground traces around these pins and to isolate them from digital lines will generally eliminate such coupling effects. In addition, optional decoupling capacitors of 1000pF or greater value can be added to VExx terminals. F. The ALD2721E/ALD2721 is designed for use in low voltage, micropower circuits. The maximum operating voltage during normal operation should remain below 10 Volts at all times. Care should be taken to insure that the application in which the device is used do not experience any positive or negative transient voltages that will cause any of the terminal voltages to exceed this limit. G. All inputs or unused pins except VExx pins should be connected to a supply voltage such as Ground so that they do not become floating pins, since input impedance at these pins is very high. If any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. As these devices are built with CMOS technology, normal operating and storage temperature limits, ESD and latchup handling precautions pertaining to CMOS device handling should be observed.
Advanced Linear Devices
ALD2721E/ALD2721

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